There are proposed various semiconductor devices in which memory cells are three-dimensionally arranged for improving the integration density of a memory. In most conventional semiconductor storage devices in which memory cells are three-dimensionally arranged, a photolithography process and a processing process such as etching need to be performed for each layer of a memory cell portion. In the conventional three-dimensionally-stacked semiconductor storage device, memory cells are simply stacked in most cases and therefore cost increase due to the three-dimensional structure is inevitable.
In most of the above described three-dimensional nonvolatile semiconductor devices, a charge storage layer is formed around a columnar semiconductor layer and it is difficult to improve a coupling ratio between the charge storage layer and a control gate electrode in a memory cell portion for each layer.